Lightweight Separation

Lightweight separation is a novel approach to automatic reasoning about memory updates in pointer programs. It replaces the spatial formulae of separation logic, which complicate automation, by independent assertions about the memory content and the memory layout. As a result, assertions about the content can be treated by existing reasoners. The effect of memory updates is evaluated using specialized tactics that prove disjointness of memory regions from a given memory layout.

Full Text (PDF)

Appears in: O. Ait Mohamed (Ed.): TPHOLs'08, LNCS 5170, pp. 199-214, 2008
Copyright by Springer-Verlag Berlin Heidelberg, 2008

Towards Verification by Symbolic Debugging

Semi-automatic or interactive software verification requires the programmer to understand the generated proof obligations by connecting them to the source code being verified. A major difficulty lies in the backward-style reasoning employed by most programming logics.

We propose that Hoare-style verification with forward reasoning is feasible and useful. The verification process appears to the user as "symbolic debugging", in which the pre-condition of a Hoare triple captures the "current state" and evolves to reflect the side-effects encountered during execution. As a result, programmers can apply their operational understanding of the program to the solving the arising proof obligations.

Extended Abstractd (PDF)

Appears in: Dennis, L.A. and Sorge, V. (Ed.): Automated Reasoning Workshop, 2008

Reasoning about Memory Layouts

Verification methods for memory-manipulating C programs need to address not only well-typed programs that respect invariants such as the split heap memory model, but also programs that access through pointers arbitrary memory objects such as local variables, single struct fields, or arrays slices. We present a logic for memory layouts that covers these applications and show how proof obligations arising during the verification can be discharged automatically using the layouts.

Full Text (PDF)

Appears in: Cavalcanti, A. and Dams, D. (Ed.): FM 2009: Formal Methods,Second World Congress. LNCS 5850. 2009
Copyright by Springer-Verlag Berlin Heidelberg, 2008

High-level reasoning about low-level programs

Functional verification of low-level code requires abstractions over the memory model to be effective, since the number of side-conditions induced by byte- addressed memory is prohibitive even with modern automated reasoners. We pro- pose a flexible solution to this challenge: assertions contain explicit memory layouts which carry the necessary side-conditions as invariants. The memory-related proof obligations arising during verification can then be solved using specialized auto- matic proof procedures. The remaining verification conditions about the content of data structures directly reflect a developer's understanding. The development is formalized in Isabelle/HOL.

Full Text (PDF)

Appears in: Roggenbach, M.: Automated Verification of Critical Systems 2009. Vol. 23, Electronic Communications of the EASST. 2009

Reasoning about Memory Layouts (Journal Version)

Verification methods for memory-manipulating C programs need to address not only well-typed programs that respect invariants such as the split-heap memory model, but also programs that access through pointers arbitrary memory objects such as local variables, single struct fields, or array slices. We present a logic for memory layouts that covers these applications and show how proof obligations arising during the verification can be discharged automatically using the layouts. The framework developed in this way is also suitable for reasoning about data structures manipulated by algorithms, which we demonstrate by verifying the Schorr-Waite graph marking algorithm.

Pre-Print (PDF)

To appear in: Formal Methods in System Design
Copyright by Springer-Verlag Berlin Heidelberg, 2011

A Developer-oriented Hoare Logic (Extended Abstract)

Extended Abstract (PDF)

Appears in: Simpson, A.: Proof Systems for Programming Logics, 2010.

Structuring Interactive Correctness Proofs by Formalizing Coding Idioms

This paper examines a novel strategy for developing correctness proofs in interactive software verification for C programs. Rather than proceeding backwards from the generated verification conditions, we start by developing a library of the employed data structures and related coding idioms. The application of that library then leads to correctness proofs that reflect informal arguments about the idioms. We apply this strategy to the low-level memory allocator of the L4 microkernel, a case study discussed in the literature.

Full Text (PDF)

To appear in: Brauer, J., Roveri, M., Tews, H.: 6th International Workshop on Systems Software Verification (SSV 2011)

Developer-oriented Correctness Proofs: A Case Study of Cheney's Algorithm

This paper examines the problem of structuring proofs in functional software verification from a novel perspective. By aligning the proofs with the operational behaviour of the program, we allow the formalization of the underlying concepts and their properties to reflect informal correctness arguments. By splitting the proof along the different aspects of the code, we achieve re-use of both theories and proof strategies across algorithms, thus enabling reasoning by analogy as employed in software construction. We demonstrate the viability and usefulness of the approach using a low-level C implementation of Cheney's algorithm.

Preprint (PDF)

To appear in: Qin, Shengchao, Qiu, Zongyan: 13th International Conference on Formal Engineering Methods (ICFEM 2011)
Copyright by Springer-Verlag Berlin Heidelberg, 2011